1. Field of the Invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells. More particularly, the present invention relates to a semiconductor integrated circuit memory device having an over-erased bit correction structure for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render improved high endurance.
2. Description of the Prior Art
As is generally known in the art, a new category of electrically erasable EPROMs/EEPROMs has emerged in recent years as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability and is sometimes referred to as "flash" EPROM or EEPROM. In these flash memories, a plurality of one-transistor flash EEPROM cells may be formed on a semiconductor substrate in which each cell is comprised of a P-type conductivity substrate, an N-type conductivity source region formed integrally with the substrate, and an N-type conductivity drain region also formed integrally within the substrate. A floating gate is separated from the substrate by a thin dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region in the substrate separates the source and drain regions.
In order to program the flash EEPROM cell in conventional operation, the drain region and the control gate are raised to predetermined potentials above the potential applied to the source region. For example, the drain region has applied thereto a voltage V.sub.D of approximately +5.5 volts with the control gate V.sub.G having a voltage of approximately +12 volts applied for approximately two or three microseconds. These voltages produce "hot electrons" which are accelerated across the thin dielectric layer and onto the floating gate. This hot electro injection results in an increase of the floating gate threshold by approximately two to four volts.
For erasing the flash EEPROM cell in conventional operation, a relatively high positive potential (i.e., +12 volts) is applied to the source region for a few tenths of a second. The control gate is grounded, and the drain region is allowed to float. A strong electric field develops between the floating gate and the source region, and negative charge is extracted from the floating gate to the source region by way of Fowler-Norheim tunneling. If an unprogrammed flash EEPROM cell in an array of such cells is repeatedly erased under these conditions, the floating gate will eventually acquire a more positive potential. Consequently, even with the control gate being grounded the cell will always be turned on which causes column leakage current thereby preventing the proper reading of any other cell in the column of the array containing this cell as well as making programming of the other cells on the same column increasingly more difficult. This condition is referred to as "bit over-erase" which is disadvantageous since the data programming characteristics of the memory cell is deteriorated so as to cause endurance failures.
An over-erased condition must be avoided in order to prevent the one-transistor flash EEPROM cell from being a depletion-like transistor in the read mode of operation. During this read mode of operation, an over-erased memory cell will disable a whole column of a memory array if these memory cells are structured as an array. As used herein, the term "endurance" refers to the number of times the memory cell may be re-programmed and erased. Consequently, the bit over-erased condition significantly reduces the endurance of the memory cell.
In order to determine whether the EEPROM cell has been properly programmed or not, the magnitude of the read current is measured. Typically, in the read mode of operation the source region is held at a ground potential (0 volts) and the control gate is held at a potential of about +5 volts. The drain region is held at a potential between 1 to 2 volts. Under these conditions, an unprogrammed cell (storing a logic "1") will conduct at a current level of approximately 50 to 100 uA. The programmed cell (storing a logic "0") will have considerably less current flowing.
There is described and illustrated in co-pending and commonly assigned Ser. No. 08/057,583 filed May 6, 1993, to M. A. Van Buskirk et al. and entitled "Flash EEPROM Array With High Endurance" an apparatus for correcting over-erased bits in an array of flash EEPROM memory cells so as to enhance its endurance. This correction of the over-erased bits occurred during the programming operation of a selected memory cell in the same column that contained the over-erased bits. The correction apparatus included a sensing circuit for detecting array column leakage indicative of an over-erased bit. When an over-erased bit was found to exist, a pulse generator would be activated so as to apply programming pulses to the control gate of the selected memory cell being programmed. Since the control gate of the non-selected memory cells in the same column containing the over-erased bit is provided with zero volts and the common source regions are tied to a ground potential, these programming pulses also serve to program back the negative threshold (-V.sub.t) of the over-erased bits to a more positive threshold.
However, this correction technique has a number of drawbacks. First, this prior art correction operation results in the application of a high voltage (i.e., +10 to +12 volts) to a control gate and a moderate voltage (i.e., +5.5 to +6 volts) to the drains of the cell being programmed. This creates a drain stress and a gate stress as well as producing an undesirable high power dissipation. A second drawback arises from the fact that additional programming pulses are being applied also to the control gate of the cell being programmed during this correction operation. This has the undesirable effect of overprogramming the cell being programmed, thereby causing endurance problems. A third drawback is caused by the correction operation being performed on a byte-wise fashion. In other words, all of the bits in the whole byte receive indiscriminately the programming pulses regardless of whether it was needed or not. This long term programming tends to degrade the conductivity of the cell being programmed.
Accordingly, there has arisen a need to provide an apparatus for correcting over-erased bits in an array of flash EEPROM memory cells on a bit-wise fashion so that only the bits in a byte being programmed which require programming receive the programming pulses, thereby eliminating the undesirable effect of overprogramming. The present invention represents a significant improvement over the aforementioned Ser. No. 08/057,583, which is hereby incorporated by reference in its entirety.